1. Field of the Invention
The present invention relates generally to a computer system addressing architecture, and more particularly to an addressing architecture which allows mapping a single memory address space onto multiple physical devices.
2. Description of the Related Art
Many computer systems provide the ability to address physical devices by assigning address ranges to each device. Operating systems and application software access system memory and other addressable devices by writing to or reading from an address in memory space. Other devices are accessed through reading and writing special addresses or xe2x80x9cportsxe2x80x9d defined in an I/O address space. An example of the former is the boot ROM; an example of the latter are modems.
In the conventional computer system, each device is typically defined at a fixed range of addresses in either memory or I/O address space, assigned by either an industry standard or a specific manufacturer. Typically, the system ROM is addressed in the 640K region immediately below 1M. Below that, systems reserve space for BIOS extensions and video RAM. Old memory management systems such as Expanded Memory Specification (EMS) used holes left in this 640K to 1M space for mapping accesses to regions above the 1M line.
Conventional memory controllers define a xe2x80x9cholexe2x80x9d into which ROMs can be mapped. Other conventional controllers allow defining attributes for certain fixed regions of memory.
Early memory controllers provided mechanisms for defining a hole in a block of RAM into which the system ROM could be addressed. More modem conventional controllers shadow (or copy) ROM code and data into that 640K to 1M space in RAM for performance reasons. However, modem controllers still provide the capability to define a hole in RAM for similar purposes. For example, one modem chip set allows defining a hole at either 512K-640K or 15M-16M. A problem with these conventional systems is that the ability to define these holes is limited to fixed specific address ranges.
A second limitation in conventional systems is the ability to define attributes to control access to certain regions of memory space. Some conventional memory controllers allow defining attributes such as write-only, read-only, and non-cacheable to a set of fixed address regions of RAM. Conventional systems typically do not flexibly define attributes to arbitrary memory regions or to ROM. Conventional systems also typically do not define areas to prevent code execution.
In a conventional system, an address which exceeds the upper limit of the addressability of a target device is typically wrapped so that addresses at the beginning of the address space are used instead. This wrapping is not always desirable.
In a system according to the preferred embodiment, a microcontroller contains an address decoder mechanism for mapping addresses in a memory address space and an I/O address space to memory and non-memory resources. The address decoder provides a number of programmable address registers for controlling a programmable address mapper. The programmable address registers and programmable address mapper provide for a flexible mechanism for assigning devices to a particular address in an address space, allowing defining attributes for controlling access to a region of address space, without requiring complicated programming.
One advantage of this mechanism is that the computer system provides compatibility with legacy computer systems, for use with DOS or WINDOWS(copyright). Further, the mechanism can provide improved flexibility in mapping devices into memory and I/O space, such as providing flexibility to overlay devices onto memory ranges and mask out the corresponding region of RAM, which would be useful to help configure multiple devices. Further, according to one aspect of an embodiment of the present invention, the mechanism provides for limiting the mapping to the addressable limit of the device.
Another advantage is the ability to define arbitrary regions of RAM or ROM to have attributes limiting the valid access to those regions. Although conventional computer systems can control the same attributes by use of a paging unit and paging tables plus a segmented code model and descriptor attributes, implementing the attribute definition mechanism in the programmable address mappers can be advantageous because the programmable address mappers are easier to use and provide greater performance. If the CPU""s paging unit is enabled, the entire system performance is degraded because all virtual addresses must be translated to physical addresses. Also, defining execution prohibited areas is difficult, requiring 48-bit code pointers and a fully segmented 32-bit code model. These performance penalties are not incurred when using the programmable address registers.